The invention relates to checking memories, and in particular to the checking of addresses used to access memories.
Errors in the address used to access a memory may result in incorrect data being retrieved from the memory. Checking logic may not detect errors in the memory itself or in the addressing lines of the memory. U.S. Pat. No. 4,271,521 to Mahmood detects errors in addressing as well as in the transfer and storage of data. Both odd and even parity are alternately assigned to data words as a function of the memory address where a particular data word is stored. A parity check is performed on both the data and address. While errors are detected, no means of correcting the errors are provided.
In U.S. Pat. No. 4,404,647 to Jones et al., two arrays contain identical data. When data is read, it is read from one of the arrays. If a data parity error is detected on readout, the other array is accessed. In this patent, no address line checking is provided. Data retrieved from a wrong address will appear to be correct.
It is an object of the invention to provide checking of addresses used to access a memory. It is a further object of the invention to provide for successfully retrying the memory in the event an error is detected. It is still a further object of the invention to provide parity on both data and address in conjunction with providing redundant copies of the data. It is yet a further object of the invention to provide a memory tolerant of having one particular address line or data access line impaired.